Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. FIG. 1 illustrates an exemplary circuit diagram of a typical six-MOS device SRAM cell, which includes pass-gate MOS devices 10 and 24, pull-up MOS devices 12 and 16, and pull-down MOS devices 14 and 18. Gates 2 and 4 of the respective pass-gate MOS devices 10 and 24 are controlled by a word-line WL that determines whether the current SRAM cell is selected. A latch formed of pull-up MOS devices 12 and 16 and pull-down MOS devices 14 and 18 stores a state. The stored state can be read through bit lines BL and BLB.
With the scaling of integrated circuits, read and write margins of the SRAM cells are reduced. Reduced read and write margins may cause errors in respective read and write operations when the read and write operations are affected by static noise. Conventionally, to improve the read and write margins, dynamic powers are provided. For example, the write margin can be improved by increasing bitline voltage and/or reducing power supply voltage VDD during the write operations, while the read margin can be improved by reducing bitline voltage and/or increasing power supply voltage VDD during the read operations. However, such a solution suffers drawbacks. Complicated circuits have to be designed to provide dynamic power for both read and write operations. Additionally, it takes time for the dynamic powers to be generated, and thus the read and write operations are slowed down.
Accordingly, a new SRAM device, having improved read and write margins while at the same time overcoming the deficiency of the prior art, is needed.